This invention relates to semiconductor fabrication processing and, more particularly, to a Complimentary Metal Oxide Semiconductor (CMOS) fabrication method for forming dual depth trench isolation for inter-well regions in semiconductor devices, such as semiconductor memory devices.
A current trend in the fabrication of CMOS devices is to use various techniques, known in the industry as xe2x80x9cshrinks,xe2x80x9d to reduce the size of the device and thus enable fabrication of a greater number of devices per each semiconductor wafer or other substrate. The rapid numbers of shrinks a given device may go through presents several challenges. Some of those challenges involve isolation between intra-well and inter-well isolation regions. Intra-well isolation is defined as the isolation between similarly doped field effect transistors. For example, n-channel field effect transistors (FETs) that reside within a common p-well region must be isolated from each other so that there is minimal interaction between the neighboring FETs. Likewise, isolation is needed between p-channel FETs that reside in a common n-well region.
Inter-well isolation is defined as the isolation between similar type dopants of a FET and a neighboring conductively doped region. For example, n-channel FETs that reside close to a neighboring n-well region require sufficient isolation to minimize the leakage current between the n-channel devices and the neighboring n-well region, that will result in isolation breakdown. Likewise, isolation is required for p-channel FETs that reside close to a neighboring p-well region.
Due to rapidly shrinking die sizes of devices, the spacing allowed for intra-well and inter-well isolation is becoming increasingly tight. The present invention provides sufficient inter-well and intra-well isolation for CMOS devices.
Exemplary implementations of the present invention comprise processes for forming dual depth trench isolation for inter-well and intra-well isolation regions in a semiconductor memory device.
An exemplary implementation of the present invention discloses a dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type for a complimentary metal oxide semiconductor device. The inter-well isolation structure comprises a stepped structure where an overlying step is wider than underlying step and the underlying step is longer (deeper) than the overlying step. The dual depth trench isolation is interposed at the boundary of an n-well conductive region and a p-well conductive region.
Additionally, the first exemplary implementation of the present invention may include a first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well region. Each intra-well isolation structure has substantially the same length (depth) as the depth of the overlying step of the inter-well isolation.
Another exemplary implementation of the present invention teaches process steps to form variations of a dual depth trench isolation structure. On exemplary process comprises, etching an inter-well trench to a first inter-well trench depth, into a conductively doped portion of a semiconductor assembly, followed by etching intra-well trenches to an intra-well trench depth on opposing sides of the inter-well trench, while simultaneously etching the inter-well trench to a second inter-well trench depth. Isolation material is then formed in the intra-well and inter-well trenches. Conductive wells that have a common boundary, but have opposite conductivity type, are formed within the conductively doped region and the isolation material is interposed at the common boundary of the conductive wells. The conductive wells (typically p-type and n-type) can be formed either before or after the isolation structures are formed. During the etching of the second inter-well trench it is preferred to consume a portion of each conductive well at their common boundary.
In yet another exemplary implementation of the present invention, the intra-wells and inter-well isolation structures are formed by a multilevel photoresist pattern with a first level defining active areas within a silicon substrate, a second level defining each intra-well width and depth, a first inter-well width and a first inter-well depth, and a third level defining a second inter-well width and a second inter-well depth. An etch step is performed that transfers the multilevel photoresist pattern to the underlying silicon substrate to form the final inter-well trench, as well as the intra-well trenches. Isolation material is then formed into the trenches to form the final inter-well and intra-well isolation structures. The conductive wells are formed as indicated previously.
The formation of the multilevel photoresist pattern comprises using gradient photolithography to impose a gradient exposure on the photoresist material or by using masks in succession to form the desired levels of the photoresist pattern.